Lead AI Engineer | Agentic AI | EDA + Semiconductor

Guri S
Lead AI Engineer

Building production agentic AI systems with LangGraph, RAG, and MCP for semiconductor R&D.

Live Demo → GitHub Research Paper LinkedIn
15+
Years Experience
5
Semiconductor Cos
3
AI Sub-Agents
1
Research Paper
Featured Project

IP Design Intelligence Agent

RAG + LangGraph Multi-Agent System for EDA

Production-grade AI agent that indexes semiconductor IP documentation and generates ECO recommendations -- deployed live on AWS Dublin.

LangGraph LangChain pgvector BM25 + RRF FastMCP A2A Protocol RAGAS LangSmith FastAPI OpenROAD sky130 PDK Docker Terraform AWS ECS

⚙ Agent Architecture

5-node LangGraph StateGraph with conditional edges, 6 bound tools, deterministic regex routing (8 rules) before LLM fallback. 3 specialist sub-agents (Timing, DRC, Physical) with cross-domain context sharing.

🔍 Hybrid RAG

pgvector semantic search + BM25 keyword search + Reciprocal Rank Fusion over semiconductor IP docs. Production ETL: download, parse, SHA256 dedup, metadata enrichment, batch embed.

🔗 MCP & A2A

FastMCP server (4 tools + 1 resource) exposing EDA search to Claude Desktop/Cursor via SSE. A2A Agent Card discovery + task delegation. 14 FastAPI REST endpoints.

🛡 Guardrails & Observability

3-layer guardrails: hallucination detection (0.3 threshold), 8-rule domain accuracy validator, format compliance. Cost router, semantic cache (0.95 cosine). LangSmith per-query tracking.

Try Live Demo → View Source API Health
Publication

Research

📚

Comparative Analysis of Retrieval Methods for RAG over EDA Documentation

G. S. Sodhi -- Zenodo, Apr. 2026 | DOI: 10.5281/zenodo.19583451

IEEE format, 12 pages, 8 figures. Benchmarks 4 retrieval methods (Vector, MultiVector, RAPTOR, ColBERT) across 3 EDA corpora. Quantifies how domain-specific chunking and metadata enrichment improve retrieval quality for semiconductor documentation.

Submitted to MLCAD 2026 IEEE Format Open Access
Career

Professional Experience

OnDev TraTech Oct 2016 -- Present
Lead AI Engineer
Bangalore, India
  • Built and shipped multiple commercial AI products end-to-end across concurrent projects. Managed team of 4-5 consultants.
  • Multi-agent AI orchestration: 3 TTS providers, 200+ neural voices, 45+ languages. LLM-powered semantic retrieval for voice matching.
  • Async ETL rendering pipeline in Python: timeline JSON to ECS Fargate worker to CloudFront CDN. Pydantic models, structured logging.
  • AI Dubbing Studio: multi-agent pipeline across 5 AI providers (Whisper, GPT-4o, Bedrock Claude, Polly, Gemini TTS) with circuit breakers.
  • Full Terraform IaC: VPC, ECS Fargate, S3, CloudFront, Lambda. AWS SigV4 signing from scratch (zero SDK dependency).
Intel Corporation Sep 2014 -- Sep 2016
Physical Design Engineer
Dublin, Ireland (Leixlip Campus) -- Quark IoT Solutions Group
  • Full semiconductor IP development: block-level P&R (500K instances), netlist to GDSII, timing closure in PrimeTime.
  • Top-level die size feasibility -- multi-instantiation block analysis, routing channel assessment.
  • EDA tool integration and database preparation: .libs/LEF for hierarchical instances, LVT cell optimization.
Nvidia Sep 2013 -- Sep 2014
Senior Physical Design Engineer
Bangalore, India -- Mobile Processor Group
  • 20nm mobile processor: 1.5M instances, 88 macros, 500MHz. Full P&R ownership, CTS optimization (200K flops).
  • Cross-site collaboration across 70-person team in 2 locations.
PMC-Sierra Apr 2009 -- Aug 2013
Senior Physical Design Engineer
Bangalore, India
  • Hierarchical block P&R (350K + 200K logic, 450MHz): MMMC flow for concurrent multi-mode/corner timing closure.
National Semiconductor Oct 2008 -- Mar 2009
Senior CAD Engineer
Greenock, Scotland, UK
  • Set up digital design flow for UK team. Block-level P&R (200K instances, 15 macros, 200MHz).
AMD Apr 2007 -- Sep 2008
Physical Design Engineer
Bangalore, India -- Graphics Processor Group
  • 65nm GPU: 600K instances, 63 macros, 600MHz. Full P&R, timing/congestion closure, SI and non-SI sign-off.
Capabilities

Technical Skills

◈ AI/ML & Agentic

LangGraph LangChain RAG Pipelines pgvector OpenAI GPT-4o AWS Bedrock Claude Google Gemini RAGAS LangSmith MCP (FastMCP) A2A Protocol

◈ Languages & Frameworks

Python FastAPI Pydantic TypeScript React 19 Swift / SwiftUI SQL Tcl Perl

◈ Cloud & Infrastructure

AWS (ECS, Lambda, S3, CloudFront) Terraform (IaC) Docker CI/CD Supabase SigV4 Auth

◈ EDA & Semiconductor

Synopsys ICC2 PrimeTime Cadence Innovus OpenSTA OpenROAD Timing Closure MMMC Physical Design
Education

Academic Background

Master of Technology -- VLSI Design & CAD

Let's Connect

Open to Lead AI Engineer, EDA + AI, and Physical Design roles.

✉ gurisai.work@gmail.com 👥 LinkedIn 💻 GitHub ⚡ Live Demo