Physical Design | STA | ASIC/SoC | AI-Assisted EDA

Guri S
Physical Design & STA Engineer

Senior silicon systems engineer — ASIC/SoC physical design, timing closure, PPA optimization and AI-assisted EDA research.

GitHub Research Paper LinkedIn
15+
Years Experience
3
Semiconductor Cos
3
AI Sub-Agents
2
Research Papers
Featured Project

IP Design Intelligence Agent

RAG + LangGraph Multi-Agent System for EDA

Production-grade AI agent that indexes semiconductor IP documentation and generates ECO recommendations -- deployed live on AWS Dublin.

LangGraph LangChain pgvector BM25 + RRF FastMCP A2A Protocol RAGAS LangSmith FastAPI OpenROAD sky130 PDK Docker Terraform AWS ECS

⚙ Agent Architecture

5-node LangGraph StateGraph with conditional edges, 6 bound tools, deterministic regex routing (8 rules) before LLM fallback. 3 specialist sub-agents (Timing, DRC, Physical) with cross-domain context sharing.

🔍 Hybrid RAG

pgvector semantic search + BM25 keyword search + Reciprocal Rank Fusion over semiconductor IP docs. Production ETL: download, parse, SHA256 dedup, metadata enrichment, batch embed.

🔗 MCP & A2A

FastMCP server (4 tools + 1 resource) exposing EDA search to Claude Desktop/Cursor via SSE. A2A Agent Card discovery + task delegation. 14 FastAPI REST endpoints.

🛡 Guardrails & Observability

3-layer guardrails: hallucination detection (0.3 threshold), 8-rule domain accuracy validator, format compliance. Cost router, semantic cache (0.95 cosine). LangSmith per-query tracking.

View Source
Publications

Research

📈

An Agentic LLM Flow for Chip Timing Closure: Cross-Stage Context Propagation in EDA

G. S. Sodhi -- Zenodo, May 2026 | DOI: 10.5281/zenodo.22019953

Empirical benchmarks on GCD, AES, and ibex (RISC-V) using real OpenROAD flows. Multi-agent architecture (TimingAgent → DRCAgent → PhysicalAgent) improved ibex WNS by +18.8 ps while single-agent worsened it by −13.0 ps. Demonstrates cross-domain context propagation prevents capacitance compounding — the dominant ECO failure mode.

Published · Zenodo Submitted to MLCAD 2026 IEEE Format
📚

Comparative Analysis of Retrieval Methods for RAG over EDA Documentation

G. S. Sodhi -- Zenodo, Apr. 2026 | DOI: 10.5281/zenodo.19583451

IEEE format, 12 pages, 8 figures. Benchmarks 4 retrieval methods (Vector, MultiVector, RAPTOR, ColBERT) across 3 EDA corpora. Quantifies how domain-specific chunking and metadata enrichment improve retrieval quality for semiconductor documentation.

Published · Zenodo Submitted to MLCAD 2026 IEEE Format
Career

Professional Experience

OnDevTra Technologies
Senior Product Specialist | AI
Gurugram / Bengaluru, India
  • Built and shipped multiple commercial AI products end-to-end across concurrent projects. Managed team of 4-5 consultants.
  • Multi-agent AI orchestration: 3 TTS providers, 200+ neural voices, 45+ languages. LLM-powered semantic retrieval for voice matching.
  • Async ETL rendering pipeline in Python: timeline JSON to ECS Fargate worker to CloudFront CDN. Pydantic models, structured logging.
  • AI Dubbing Studio: multi-agent pipeline across 5 AI providers (Whisper, GPT-4o, Bedrock Claude, Polly, Gemini TTS) with circuit breakers.
  • Full Terraform IaC: VPC, ECS Fargate, S3, CloudFront, Lambda. AWS SigV4 signing from scratch (zero SDK dependency).
Independent Software Consultant
Apple Platforms & Full-Stack Systems
Bengaluru, India
  • Delivered independent software and product-engineering engagements centered on iOS/iPadOS applications and connected backend services, using Swift/SwiftUI, API-driven architecture and cloud integrations.
  • Translated product requirements into software architecture, data models, API contracts, UI/UX flows and implementation plans.
  • Implemented production features including subscriptions/payment flows, account and entitlement logic, media workflows and App Store release support.
Intel Corporation
Physical Design Engineer
Dublin, Ireland (Leixlip Campus) -- Quark IoT Solutions Group
  • Full semiconductor IP development: block-level P&R (500K instances), netlist to GDSII, timing closure in PrimeTime.
  • Top-level die size feasibility -- multi-instantiation block analysis, routing channel assessment.
  • EDA tool integration and database preparation: .libs/LEF for hierarchical instances, LVT cell optimization.
Nvidia
Senior Physical Design Engineer
Bangalore, India -- Mobile Processor Group
  • 20nm mobile processor: 1.5M instances, 88 macros, 500MHz. Full P&R ownership, CTS optimization (200K flops).
  • Cross-site collaboration across 70-person team in 2 locations.
PMC-Sierra
Senior Physical Design Engineer
Bangalore, India
  • Hierarchical block P&R (350K + 200K logic, 450MHz): MMMC flow for concurrent multi-mode/corner timing closure.
Read VLSI & Physical Design Blogs →
Capabilities

Technical Skills

◈ AI/ML & Agentic

LangGraph LangChain RAG Pipelines pgvector OpenAI GPT-4o AWS Bedrock Claude Google Gemini RAGAS LangSmith MCP (FastMCP) A2A Protocol

◈ Languages & Frameworks

Python FastAPI Pydantic TypeScript React 19 Swift / SwiftUI SQL Tcl Perl

◈ Cloud & Infrastructure

AWS (ECS, Lambda, S3, CloudFront) Terraform (IaC) Docker CI/CD Supabase SigV4 Auth

◈ EDA & Semiconductor

Synopsys ICC2 PrimeTime Cadence Innovus OpenSTA OpenROAD Timing Closure MMMC Physical Design
Education

Academic Background

Master of Technology -- VLSI Design & CAD

Let's Connect

Open to Physical Design, STA, ASIC implementation and EDA + AI roles.

✉ Contact Me 👥 LinkedIn 💻 GitHub