VLSI Physical Design & STA Blog

Technical articles on ASIC physical implementation, timing closure, low power design and AI-assisted EDA.

Clock Skew, Setup & Hold Explained with a Town Traffic Analogy

Derive positive/negative skew effects from first principles. Town-traffic analogy, formal equations, worked numerical examples, and common interview mistakes.

STA / OCV

OCV Derating & CPPR — Data Path vs Clock Path Pessimism

Why CPPR only helps when clock paths are derated — worked examples, AOCV vs POCV at advanced nodes, CPPR credit calculation, and PrimeTime/Tempus commands for sign-off.

AI Silicon

From Transformer Math to Physical Silicon — Designing an LLM AI Accelerator

How LLM workloads translate into silicon: tensor compute architecture, prefill vs decode, routing congestion, IR drop, thermal hotspots, and physical design solutions.

Power Grid

Power Grid Design: Meshes, Via Stacks, Rails & Level Shifters

How power physically reaches standard cells — from package bumps through upper-metal meshes, stacked vias, M1 rails, and dual-rail level shifters in multi-voltage SoCs.

STA / Timing

MCMM Timing Closure at Advanced Nodes

Strategies that actually work — OCV/AOCV/POCV derating, cross-corner CTS balancing, useful skew, ECO flows, and real WNS/TNS numbers from tapeouts.

Low Power

Low Power Design in VLSI — Challenges & Solutions

Power gating, UPF, multi-Vt optimization, clock gating, DVFS — practical techniques with real power reduction numbers from production tapeouts.