OCV Derating & CPPR — Data Path vs Clock Path Pessimism

Every physical design engineer encounters this question in interviews and on the job: "If I apply OCV derating only on the data path, does CPPR help?" The answer is no — and understanding why reveals the fundamental distinction between data-path pessimism and clock-path pessimism that underpins all of modern STA sign-off.

This post breaks down OCV derating mechanics, explains exactly when and why CPPR (Common Path Pessimism Removal, also called CRPR — Clock Reconvergence Pessimism Removal) provides a timing credit, and covers the progression from flat OCV through AOCV and POCV at advanced nodes.

Why We Need OCV Derating

OCV stands for On-Chip Variation. Even on the same die, cell and interconnect delays vary because of:

• Process variation — lithographic dose, etch bias, and CMP non-uniformity create local gate-length and threshold-voltage differences
• Voltage variation — IR drop and Ldi/dt create localized supply droop that differs by tens of millivolts across the die
• Temperature variation — hotspots near high-activity blocks create on-die thermal gradients of 10-20°C
• Local RC variation — metal width/thickness variation and via resistance differences in back-end layers
• Aging effects — BTI (Bias Temperature Instability) and HCI (Hot Carrier Injection) degrade specific transistors over time

STA cannot trust a single nominal delay. Instead, it applies conservative derating factors to model the worst-case variation. For a setup check, data is made artificially slow (late derate) so we have confidence the design works even under on-die variation.

The Simplified Timing Path

Consider this standard register-to-register path:

CLK (source)
 +-- CKBUF8 (common clock path)
      |
      +-- CKBUF4 (launch branch) --> Launch FF
      |
      +-- CKBUF4 (capture branch) --> Capture FF

Launch FF /Q --> U1 --> U2 --> U3 --> Capture FF /D

The clock path contains only clock cells: CKBUF8, CKBUF4. The data path contains only combinational logic: U1, U2, U3. These are separate domains from an OCV perspective, and understanding that distinction is the key to understanding CPPR.

Data-Path OCV Derating: A Worked Example

Assume nominal data path delays:

U1 = 80 ps
U2 = 120 ps
U3 = 60 ps
-------------------
Nominal data path = 260 ps

Apply a late derate of 1.10 (10% pessimism for setup analysis):

Derated data path = 260 x 1.10 = 286 ps

Now calculate setup slack:

Clock period   = 500 ps
Setup time     = 20 ps
Clock skew     = 0 ps

Required time  = 500 - 20 = 480 ps
Arrival time   = 286 ps

Slack = 480 - 286 = +194 ps

When Does CPPR Actually Help?

CPPR becomes relevant when both clock and data paths are derated — which is the standard practice at sign-off. For a setup check, STA applies:

• Launch clock → late derate (makes launch arrive later, helping setup)
• Data path → late derate (makes data arrive later, hurting setup)
• Capture clock → early derate (makes capture arrive earlier, hurting setup)

The problem: launch and capture clocks share the same physical cells from the clock source to the split point. STA treats the common clock segment as late for launch and simultaneously early for capture. This is physically impossible — the same buffer cannot be both fast and slow for the same clock edge.

CPPR Credit Calculation

Consider a common clock path from CLK source through CKBUF8 to the split point:

Common clock path nominal delay = 200 ps

For setup analysis:
  Launch (late derate 1.10): common path = 200 x 1.10 = 220 ps
  Capture (early derate 0.90): common path = 200 x 0.90 = 180 ps

Artificial pessimism on common path:
  Launch sees 220 ps, Capture sees 180 ps
  Difference = 220 - 180 = 40 ps of FALSE pessimism

CPPR credit = 40 ps (added back to slack)

Without CPPR, the tools report 40 ps of extra pessimism that does not exist in silicon. On a design with thousands of timing-critical paths, this false pessimism can mean the difference between meeting timing and requiring costly logic restructuring or frequency reduction.

Setup vs Hold CPPR

For hold checks, the pessimism is reversed: the common path is treated as early for launch and late for capture. CPPR removes that difference as well.

Flat OCV vs AOCV vs POCV

The evolution of OCV modeling reflects the semiconductor industry's need for less pessimistic (but still safe) sign-off methodologies at advanced nodes:

Flat OCV

A single derate factor (e.g., ±8%) applied uniformly to all cells and nets regardless of path depth or location. Simple but overly conservative — it treats a 3-stage path and a 30-stage path identically, despite the fact that variation averages out statistically over longer paths.

# PrimeTime: Flat OCV setup
set_timing_derate -early 0.92 -cell_delay -net_delay
set_timing_derate -late  1.08 -cell_delay -net_delay

# Clock network (tighter derates — better controlled)
set_timing_derate -early 0.95 -clock
set_timing_derate -late  1.05 -clock

AOCV (Advanced OCV)

Derate factors vary by path depth (number of stages) and distance (physical separation between endpoints). A path through 20 stages gets a smaller per-stage derate than a path through 3 stages because random variation averages out over more elements — the Central Limit Theorem applied to timing.

# PrimeTime: AOCV setup
read_aocvm ./lib/aocv_ss_0p72v_125c.aocvm

# Cadence Tempus:
set_aocv_derate -aocv_file ./lib/aocv_table.aocvm

AOCV typically recovers 30-50 ps of margin on critical paths compared to flat OCV. The foundry provides AOCV tables indexed by (cell_type, depth, distance).

POCV / SOCV (Parametric / Statistical OCV)

The most accurate method. Each cell arc has its own Gaussian delay distribution characterized by mean and sigma. Path-level variation is computed by RSS (root-sum-square) of individual stage sigmas, then an N-sigma multiplier (typically 3-sigma) determines the derate. This correctly models that random variations are uncorrelated across cells.

# PrimeTime: POCV setup
set_app_var timing_pocvm_enable_analysis true
read_pocvm ./lib/pocv_ss_0p72v_125c.pocvm

# Or via Liberty Variation Format (LVF)
read_lvf ./lib/ss_0p72v_125c.lvf

# Cadence Tempus:
set_db timing_analysis_type pocvm

POCV recovers an additional 20-40 ps versus AOCV on critical paths. At 5nm and 3nm, POCV is mandatory at sign-off — flat OCV would impose 12-15% derates that result in excessive area and power overhead from over-fixing.

EDA Tool Commands Reference

Synopsys PrimeTime

# Enable CPPR
set_app_var timing_remove_clock_reconvergence_pessimism true

# Report CPPR credit on a specific path
report_timing -path_type full_clock_expanded -cppr

# Report CRPR for all violating paths
report_crpr -slack_lesser_than 0

# OCV derating
set_timing_derate -early 0.93 -late 1.07 -cell_delay
set_timing_derate -early 0.97 -late 1.03 -clock

# POCV
set_app_var timing_pocvm_enable_analysis true
read_pocvm ./pocv_table.pocvm

# AOCV
read_aocvm ./aocv_table.aocvm

Cadence Tempus

# Enable CPPR for both setup and hold
set_analysis_mode -cppr both

# Set OCV derates
set_timing_derate -early 0.93 -late 1.07 -cell_delay
set_timing_derate -early 0.97 -late 1.03 -clock_delay

# AOCV
set_aocv_derate -aocv_file ./aocv_table.aocvm

# Report with CPPR details
report_timing -path_type full_clock -cppr_info

CPPR and MCMM Sign-off

Each MCMM corner already captures global process/voltage/temperature variation. OCV models local within-die variation on top of that global shift. Best practice at sign-off:

• Apply OCV at every sign-off corner independently — variation magnitudes differ by corner
• POCV sigma values are corner-specific — variation is larger at extreme corners (foundries provide per-corner POCV libraries)
• Always enable CPPR — without it, you are leaving 30-80 ps of false pessimism on every path with shared clock tree
• Worst setup is typically at the slow corner with late-derate on data + early-derate on capture clock
• Worst hold is critical at fast corners where early-derate on data makes paths dangerously short

Common Interview Questions

Q: "What is CPPR and when does it apply?"

CPPR removes false pessimism that arises when STA applies opposite early/late derates to the same physical clock cells on the common clock path. It applies whenever launch and capture clocks share clock-tree elements and OCV derating is active on the clock network. It does NOT apply when only the data path is derated.

Q: "Can CPPR credit be negative?"

No. CPPR credit is always zero or positive (beneficial). If there is no common clock path, or if clock derating is not applied, the credit is simply zero.

Q: "Why is POCV better than flat OCV?"

Flat OCV applies the same percentage to all paths regardless of length. Statistically, random variation averages out over longer paths (Central Limit Theorem). POCV models this correctly by computing per-cell sigma and combining them via RSS, resulting in less pessimism on long paths while maintaining safety on short paths.

Q: "Does CPPR apply to AOCV/POCV flows?"

Yes. CPPR is orthogonal to the derating method. Whether you use flat OCV, AOCV, or POCV, the common clock path still receives conflicting early/late treatment. CPPR removes that structural pessimism regardless of which variation model generates the derates.

Summary

The one-liner: OCV derating is the broad mechanism that models on-die variation. CPPR is specifically a common-clock-path correction that removes the physically impossible scenario of the same clock buffer being both fast and slow simultaneously.